Digital Fundamentals Instructor Guide: FPGA Beer Module
Description:
The materials for this FPGA Beer Module lab activity are provided by Maricopa Advanced Technology Education Center (MATEC). The goal of this lab is to '"earn the use of Spartan 3E FPGA development board from Xilinx and how to create the hardware connections between the development board and your PC." Learning objectives for this lab include:
- Getting familiar with Spartan 3E FPGA board. The advantage of this board is programmed through USB port. JTAG port is used to program previous versions.
- Implement the VHDL and User Constraint File "ucf" that maps the input and output signals to the Spartan 3E FPGA using Xilinx(R) ISE 9.2i, compile and simulate for Xilinx Spartan 3E FPGA
- Test the Results
- Compare your results with the traditional way of TTL technology and bread boarding.
Contents:
Materials for this module include a Lab: Operation of Pasteurization Process Control instructor guide and other files related to the lab activity.
The 20-page Lab Operation of Pasteurization Process Control instructor guide provides an overview of the lab activity and covers the following topics: Purpose, Systems Rationale, System Concepts, Learning Outcomes, Learning Objectives, and more.
For orientation purposes Beer_Project.pdf is included as a separate attachment and provides a detailed description of the course.
FPGA Beer Module (30 files, 11.2 MB)
- Beer Module Documents (4 files, 5.6 MB)
- (BEER PROJECT SlowClock.vhd 3KB)
- Lab: Operation of Pasteurization Process Control (Beer Project.doc 5.6 MB)
- (BEER.ucf 439 bytes)
- Beer Module FPGA Sound Files (25 files, 5.6 MB)
- (37MAMBO.MID 24 KB)
- (alarm.wav 26 KB)
- (Beer Model.exe 119 KB)
- (chillerON.wav 22 KB)
- (clockChimes.wav 18 KB)
- (Cold.wav 129 KB)
- (Empty.wav 113 KB)
- (Excellent.wav 159 KB)
- (filling-heineken.wav 107 KB)
- FPGA Beer Module (29 files, 7.2 MB)
- Beer Module FPGA Sound Files (24 files, 1.4 MB)
- (37MAMBO.MID 24 KB)
- (alarm.wav 26 KB)
- (Beer Model.exe 119 KB)
- (chillerON.wav 22 KB)
- (clockChimes.wav 18 KB)
- (Cold.wav 129 KB)
- (Empty.wav 113 KB)
- (Excellent.wav 159 KB)
- (filling-heineken.wav 107 KB)
- (Full 1.wav 155 KB)
- (full.WAV 19 KB)
- (HeaterON.wav 27 KB)
- (Hot.wav 150 KB)
- (inletClose.wav 6 KB)
- (inletOpen.wav 44 KB)
- (open-heineken.wav 46 KB)
- (productFrozen.wav 26 KB)
- (Siren.wav 36 KB)
- (thank you.wav 5KB)
- (Winlo.dll 49 KB)
- (Winlo.sys 5KB)
- (WINLO.VXD 5KB)
- (zFull.wav 158 KB)
- Beer Module Documents (4 files, 5.6 MB)
- (BEER PROJECT SlowClock. vhd 3KB)
- (Beer Project.doc 5.6 MB)
- (BEER.ucf 439 bytes)
- Beer Module FPGA Sound Files (24 files, 1.4 MB)
- (Full 1.wav 155 KB)
- (full.WAV 19 KB)
- (HeaterON.wav 27 KB)
- (Hot.wav 150 KB)
- (inletClose.wav 6 KB)
- (inletOpen.wav 44 KB)
- (open-heineken.wav 46 KB)
- (productFrozen.wav 26 KB)
- (Siren.wav 36 KB)
- (thank you.wav 5KB)
- (Winlo.dll 49 KB)
- (Winlo.sys 5KB)
- (WINLO.VXD 5KB)
- (zFull.wav 158 KB)
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